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W25Q128BV
7.2.12 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except
that data is output on two pins; IO 0 and IO 1 . This allows data to be transferred from the W25Q128BV at
twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly
downloading code from Flash to RAM upon power-up or for applications that cache code-segments to
RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of F R (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24 -bit address as shown in Figure 11. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy clocks
is “don’t care”. However, the IO 0 pin should be high-impedance prior to the falling edge of the first data
out clock.
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
CLK
Mode 0
Instruction (3Bh)
24-Bit Address
DI
(IO 0 )
23
*
22
21
3
2
1
0
DO
(IO 1 )
/CS
* = MSB
High Impedance
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
CLK
Dummy Clocks
IO 0 switches from
Input to Output
DI
(IO 0 )
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
DO
(IO 1 )
High Impedance
7
*
5 3
Data Out 1
1
7
*
5 3
Data Out 2
1
7
*
5 3
Data Out 3
1
7
*
5 3
Data Out 4
1
7
Figure 11. Fast Read Dual Output Instruction Sequence Diagram
- 28 -
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